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Ordering number:ENN 4144
*
CMOS IC
LC573104A, 573102A
4-bit Single Chip Microcontroller
Preliminary Overview
LC573104A and LC573102A are CMOS 4-bit microcontrollers featuring low-voltage operation and low power dissipation. Both LC573104A and LC573102A incorporate a 4-bit parallel processing ALU, 4K bytes/2K bytes ROM, a 64x4-bit RAM, a 16-bit timer, and an infrared remote control transmission carrier output circuit.
Package Dimensions
unit:mm 3112A-MFP24S
[LC573104A, 573102A]
24 13
5.4
Applications
12.5 0.15
0.1 1.5 0.63
1
12
Features
* ROM : 4096x8 bits (LC573104A) 2048x8 bits (LC573102A) * RAM : 64x4 bits * Cycle time
Cycle time 17.6s System clock generator Ceramic oscillation circuit Oscillation frequency 455kHz Supply voltage 2.3 to 6.0V
0.35
1.0
(0.75)
1.7max
* Remote controller. * Control of small measuring instruments.
SANYO : MFP24S
Pin Assignment
* Current Drain a. At normal operation
Current drain 150A typ 400A typ System clock generator CR oscillation CR oscillation Oscillation frequency 455kHz 455kHz Supply voltage 3.0V 5.0V
b. HALT mode
Current drain 80A typ 300A typ System clock generator CR oscillation CR oscillation Oscillation frequency 455kHz 455kHz Supply voltage 3.0V 5.0V
c. HOLD mode
Leakage current 0.1A typ Condition When CR oscillation is at STOP mode Oscillation frequency 455kHz Supply voltage 5.0V
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges,or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
O1501TN (KT)/13195JN/5252JN No.4144-1/16
7.6
LC573104A, 573102A
* Port * Input port (S port, M port) : * Input/Ouput port : P0 port, P1 port P2 port 2-port (8 pins) [Key scan input port] 3-port (10 pins) 2-port (8 pins) [Key scan output port] 1-port (2 pins) [Key scan expansion port] [LED direct drivable port] * Infrared remote control carrier generation circuit. * Software-controllable remote control carrier output ON/OFF. * Software-controllable carrier frequency and duty ratio. <38kHz-1/3 duty, 38kHz-1/2 duty, 57kHz-1/2 duty> (When fixed carrier signal is output, it is specified by mask option) * 1kHz to 200kHz infrared remote control transmission carrier frequency. (When carrier output is selected by timer at mask option, and when 455kHz CR oscillator is used) * Infrared carrier output-dedicated terminal built-in (CA terminal). * 108ms HALT-mode cancel signal output. * Timer * 16-bit software-controllable Timer Timer input clock : Ceramic (CR) oscillation frequency (455kHz). * 108ms HALT release request signal generation timer (Free running timer). * Watchdog timer (changed over between USED/UNUSED by mask option) * Sub-routine stack level * 2 levels * Oscillation circuit * Ceramic (CR) oscillation circuit : 455kHz (for System clock generation), Feedback resistor built-in. * Standby function * HALT mode HALT mode used to reduce current drain. HALT mode suspends program execution. Following shows how to release the HALT mode. (A) System reset (B) HALT mode release request signal. * HOLD mode HOLD mode stops ceramic resonator (CR). The HOLD mold can be released in two ways. (A) System reset (B) Apply H level input to S port pin or M port pin. (However, it is necessary to set S port or M port HOLD mode release permission flag beforehand.) * From of shipment * MFP-24S (1.0mm pitch) and chip. NOTE : When dipping in solder to mount the MFP package on board, contact SANYO for instructions.
No.4144-2/16
LC573104A, 573102A
The Application Development System for the LC573100 Series. (1) Manual (A) Users Manual : LC573100 Series Users Manual. (B) Development Tool Manual : LC573100 Series Development Tool Manual. (2) Development Tools * Tools for application development of the LC573100 Series. (A) Personal computer (MS-DOS based). (B) Cross assembler (LC573100.EXE). (C) Mask option generator (SU573100.EXE). * Tools to evaluate application development of the LC573100 Series. (A) EVA chip (LC5797). NOTE 1) As RAM capacity differs between EVA chip (LC5797) and the LC573100 Series, always check before programming and debugging. LC573100 : 64x4 bits LC5797 : 256x4 bits NOTE 2) Always keep the DPH value in mind when programming. Only DPH `0' to `3' may be used as the RAM address. If DPH other than `0' to `3' is used as RAM address when programming, SANYO will not be liable for any trouble caused. (B) EVA chip board (TB5730). NOTE) The application evaluation board is the evaluation board made by the user. (C) Evaluation board [EVA420 (Monitor ROM : ER-573000)] (D) Display and mask option data control board [DCB-1A (REV3.6)]
Development Support System Outline
Do not cross or twist these cables.
No.4144-3/16
LC573104A, 573102A
(A) Block Diagram (LC573104A)
No.4144-4/16
LC573104A, 573102A
Die Specifications Chip size : Chip thickness : Pad size : Pad Layout
3.51mmx3.19mm 480m 120mx120m
Pad coordinates
MFP24S pin assignment Pad Pin X No. Name (m) 17 1465 1 VDD 18 1155 2 CA 19 - 305 3 P20 20 - 1485 4 P21 21 - 1485 5 P00 22 - 1485 6 P01 23 - 1485 7 P02 24 - 1485 8 P03 1 - 1485 9 P10 2 - 1485 10 P11 3 - 1485 11 P12 4 - 1485 12 P13 5 - 410 13 S1 Y (m) 1365 1365 1365 1365 1110 870 565 325 20 - 220 - 480 - 1395 - 1395 MFP24S pin assignment Pad Pin X No. Name (m) 6 360 14 S2 7 560 15 S3 8 760 16 S4 - 960 17 TEST - 1140 18 TEST 9 1560 19 M1 10 1560 20 M2 11 1560 21 M3 12 1560 22 M4 13 1465 23 RES 14 1465 24 VSS 15 1465 25 CF1 16 1465 26 CF2 Y (m) - 1395 - 1395 - 1395 - 1395 - 1395 - 1395 - 905 - 685 - 445 330 570 755 1155
* The chip center is the origin of the above pad coordinates. The X, Y values represent the coordinate of the pad center. * When dipping the MFP24S package in solder to mount on boards, contact SANYO for instructions, etc. * Chip substrate should be connected to VSS or left open.
No.4144-5/16
LC573104A, 573102A
Pin Function
MFP24S Pin Pin No. name 17 VDD 14 VSS 15 16 5 6 7 8 9 10 11 12 21 22 23 24 1 2 3 4 19 20 CF1 CF2 S1 S2 S3 S4 M1 M2 M3 M4 P00 P01 P02 P03 P10 P11 P12 P13 P20 P21 Input/ Input/ Input/ Input/output port. * Output pin to output data from accumulator. (P-ch Open Drain Output) Input/output port. * Output pin to output data from accumulator. (P-ch Open Drain Output) Input/output port. * Output pin to output data from accumulator. (P-ch Open Drain Output) * LED direct drivable pin. 18 CA Output Remote control carrier output. Fixed carrier output/ Carrier output by timer 13 RES Input Reset input. Internal pull-up resistor. * At reset 'L' level. * At fixed carrier output 38kHz-1/3 duty. Output * Data loaded in accumulator. Output * Data loaded in accumulator. Output * Data loaded in accumulator. Input Input/ Function description Output - Supply voltage. See Fig 1. - Input Ground. See Fig 1. User for system clock oscillation. * 455kHz ceramic resonator is connected between CF1 and Output CF2 for oscillation. * Stops oscillation when receiving CR oscillation stop command. Input Input port S. * LSI system is reset by charging VDD to S1 to S4 simultaneously (Mask option). * Data is loaded in accumulator. Input port M. Data loaded in accumulator. 'L' level HOLD Tr YES/NO * Pull-down resistor ON. (1) 'L' level HOLD Tr YES/NO (2) Reset by S1 to S4. * Pull-down resistor ON. * Reset signal ENABLE. Option Reset status
No.4144-6/16
LC573104A, 573102A
Supply connections
Fig. 1 Supply connections
No.4144-7/16
LC573104A, 573102A
Mask Option (1) Input port option
Option 'L' level Hold Tr selection Circuit sequence. * S1 to S4, M1 to M4 Input signal level Hold Tr selection * 'L' level Hold Tr used. * 'L' level Hold Tr not used. Remarks Next port switches over in
(2) Reset signal option by S port
Option Resetting IC by S port Circuit Remarks Selects signal for resetting IC system by simultaneously charging 'H' level to S1 to S4. * Allow * Prohibit
(3) Carrier standard clock generation circuit option for remote control
Option 38/57kHz Circuit Remarks Software-controllable carrier frequency and duty. * Following carrier frequency and duty may be selected by setting control register 4. (1) 38kHz-1/3 Duty (2) 38kHz-1/2 Duty (3) 57kHz-1/2 Duty
Timer 8 bit overflow
Timer 8-bit overflow signal generates carrier signal for infrared remote control.
No.4144-8/16
LC573104A, 573102A
(4) Watchdog timer circuit option
Option Watchdog timer selection Circuit selection Remarks Watchdog timer used/unused
Specifications
Absolute Maximum Ratings
Parameter Supply voltage Symbol VDD VDD1 VDD2 Input voltage Output voltage VIN VOUT IOUT1 Output current (Per 1 pin) IOUT2 IOUT3 IOUT4 Total output current of all pins except CA Operating temperature Storage temperature IALL Topr Tstg S1 to S4, M1 to M4, RES, P00 to P03, P10 to P13, P20, P21, CF1 (P00 to P03, P10 to P13, P20, P21 are input mode) CA, P00 to P03, P10 to P13, P20, P21, CF2 (P00 to P03, P10 to P13, P20, P21 are output mode) CA (per 1 pin) P00 to P03, P10 to P13 (per 1 pin) P20, P21 (Per 1 pin) Output pins other than listed above (per 1 pin) All pins totaled (except for CA pin) Conditions Ratings -0.3 to +7.0 -0.3 to VDD -0.3 to VDD -0.3 to VDD+0.3 -0.3 to VDD+0.3 25 500 10 500 25 -30 to +70 -40 to +125 Unit V V V V V mA A mA A mA
C C
Recommended Operating Ranges at Ta =-30 to +70C, VSS=0V
Parameter Supply voltage Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Operation frequency Symbol VDD VIH1 VIL1 VIH2 VIL2 fOPG Conditions Ratings min 2.3 S1 to S4, M1 to M4, P00 to P03, P10 to P13, P20, P21 (P0, P1, P2 ports are input mode) RES At CR oscillation, Fig. 2
0.7VDD
typ
max 6.0 VDD
0.3VDD
Unit V V V V V kHz
0
0.75VDD
VDD
0.25VDD
0 380 455
500
Fig. 2 CR Oscillation Circuit
No.4144-9/16
LC573104A, 573102A
Electrical Characteristics at Ta =-30 to +70C, VSS=0V
Parameter Symbol RIN1A Input impedance RIN1B RIN2 VOH1 IOFF IOFF VOH2 IOFF IOFF IOH1 IOL1 IDD1 IDD2 ILEAK1 ILEAK2 VST VSUS tST Conditions VDD=2.9V, VIL=0.4V, S1 to S4, M1 to M4, 'L' level Hold Tr, Fig. 3 VDD=2.9V, VIL=0.4V, S1 to S4, M1 to M4, 'L' level pull-down Tr, Fig. 3 VDD=2.9V, RES VDD=2.9V, IOH=-450A, P00 to P03, P10 to P13 VIN=VSS VDD=2.9V, P00 to P03, P10 to P13 VIN=VDD VDD=2.9V, IOH=-10mA, P20, P21 VDD=2.9V, P20, P21 VDD=3.0V, VOH=VDD-1.5V, CA VDD=3.0V, VOH=0.9V, CA VDD=3.0V, 455kHz CR oscillation, Ccd=Ccg=150pF, Ta50C, Fig.5 VDD=3.0V, 455=kHz CR oscillation, Ccd=Ccg=150pF, Ta50C, Fig.5 VDD=3.0V Ta=25C Ta=50C 2.0 30 VIN=VSS VIN=VDD -1.0 6 2 12 5 80 150 0.2 1 300 500 1 5 2.3 Ratings min 150 30 10
VDD-0.45
typ 300 50
max 1000 100 300 1.0
Unit k k k V A A V
Output high-level voltage Output off-leak current Output high-level voltage Output off-leak current Output current (H) Output current (L) HALT-mode supply current Operating current Supply leak current 1 Supply leak current 2 Oscillator start-up voltage Oscillator sustaining voltage Oscillator start-up time
-1.0 VDD-0.5 1.0
A A mA mA A A A A V V ms
Ccd=Ccg=150pF, 455kHz CR oscillation, Fig. 4 VDD=2.3V, Ccd=Ccg=150pF, 455kHz CR oscillation, Fig. 4
Recommended Oscillators.
Oscillator Manufacturer Part number KBR-455BK/Y CSB455E POE-455 Ccg 150pF 150pF 150pF Ccd 150pF 150pF 150pF 455kHz ceramic Kyocera oscillator Murata Fuji Ceramics
Electrical Characteristics at Ta =-30 to +70C, VSS=0V
Parameter Symbol RIN1A Input impedance RIN1B RIN2 VOH1 IOFF IOFF VOH2 IOFF IOFF IOH1 IOL1 IDD1 IDD2 ILEAK1 ILEAK2 VST VSUS tST Conditions VDD=5.0V, VIL=0.4V, S1 to S4, M1 to M4, 'L' level Hold Tr, Fig. 3 VDD=5.0V, S1 to S4, M1 to M4, 'L' level pull-down Tr, Fig. 3 VDD=5.0V, RES VDD=5.0V, IOH=-750A, P00 to P03, P10 to P13 VIN=VSS VDD=5.0V, P00 to P03, P10 to P13 VIN=VDD VDD=5.0V, IOH=-10mA, P20, P21 VDD=5.0V, P20, P21 VDD=5.0V, VOH=VDD-2.5V, CA VDD=5.0V, VOL=0.9V, CA VDD=5.0V, 455kHz CR oscillation, Ccd=Ccg=150pF, Ta50C, Fig.5 VDD=5.0V, 455kHz CR oscillation, Ccd=Ccg=150pF, Ta50C, Fig.5 VDD=5.0V Ta=25C Ta=50C 2.0 30 VIN=VSS VIN=VDD -1.0 10 2 20 5 300 400 0.2 1 400 500 1 5 2.3 Ratings min 70 30 10
VDD-0.75
typ 200 50
max 600 100 300 1.0
Unit k k k V A A V
Output high-level voltage Output off-leak current Output high-level voltage Output off-leak current Output current (H) Output current (L) HALT-mode supply current Operating current Supply leak current 1 Supply leak current 2 Oscillator start-up voltage Oscillator sustaining voltage Oscillator start-up time
-1.0 VDD-0.5 1.0
A A mA mA A A A A V V ms
Ccd=Ccg=150pF, 455kHz CR oscillation, Fig. 4 VDD=2.3V, Ccd=Ccg=150pF, 455kHz CR oscillation, Fig. 4
No.4144-10/16
LC573104A, 573102A
Fig. 3 : S1 to S4, M1 to M4 input structure Fig. 4 : Oscillator start-up voltage, Oscillator sustaining voltage, and Oscillator start-up time measuring circuit.
Note : CR is 455kHz, S-PORT : M-PORT : Input lead Tr is ON. RES terminal has resistor built-in and is OPEN. I/O-PORT is set at Output Mode and data is `H'.
Fig. 5 : Supply current measuring circuit
LC573100 Series Instruction Set The instruction set uses the following abbreviations and symbols. AC ACn CF DP DPL DPH EDP EDPL EDPH SP TREG SCFn CTLn HEFn ROM CFCF () [] : Accumulator : Accumulator bit n : Carry flag : Data pointer : Data pointer low nibble : Data pointer high nibble : Data pointer save register : Data pointer save register low nibble : Data pointer save register high nibble : Strobe pointer : Temporary register : Start conditioning flag n : Control register n : Hold enable flag n : ROM data : Ceramic resonator oscillator control flag : Contents : Contents : Logical OR : Logical exclusive-OR : Logical AND : Transfer direction, result M M (DP) [M (DP)] PC PCn PAGE STSn (STSm) [P ( )] X Xn PDF SFR (SFR) CSTF SPC CCF () [] n WDT : Memory : Memory addressed by DP : Contents of memory addressed by DP : Program counter : Program counter bit n : Page latch : Status register n : Status register n content : Contents of port ( ) : Immediate data : Immediate data bit n : Input port pull-down flag : Special function register : Contents of special function register : Chrono start flag : Strobe pointer control bit : Carrier output control flag : Complement of contents : Complement of contents : Output from stage n of 15-stage divider : Watchdog timer
<
* The special function registers are abbreviated as follows. TCON : Timer control register TLOW : Timer/counter register low byte THIGH : Timer/counter register high byte CTL4 : Control register 4 P0 : Port P0 P1 : Port P1 P2 : Port P2
No.4144-11/16
LC573104A, 573102A
LC573100 Series Instructions
Instruction
Mnemonic TAAT MTR ASR0 ASR1 ASL0 ASL1 INC DEC ADC ADC* ADCI X SBC SBC* SBCI X ADD Instruction code 0000 0001 0001 0001 0001 0001 1001 1001 1000 1000 1001 ---- 1000 1000 1001 ---- 1000 1000 1001 ---- SUB SUB* SUBI X ADN ADN* ADNI X AND AND* ANDI X EOR EOR* 1000 1000 1001 ---- 1000 1000 1001 ---- 1000 1000 1001 ---- 1000 1000 1001 ---- 1000 1000 1001 ---- 0001 0010 1000 1001 1010 1011 1000 1001 0000 1000 Function AC, TRGE ROM M (DP) TREG ACn ACn+1, AC3 0 ACn ACn+1, AC3 1 ACn ACn-1, AC0 0 ACn ACn-1, AC0 1 AC, M (DP) M (DP)+1 AC, M (DP) M (DP)-1 AC (AC)+[M (DP)]+CF AC, M (DP) (AC)+[M (DP)]+CF
Cycles
Bytes
Status Function description Contents of ROM on current page, addressed by PC whose low-orderd 8 bits are replaced with contents of AC and M (DP), are loaded to AC and TREG Stores the conternts of TREG memory location pointed to by DP. Shifts the contents of the AC right and enter 0 into the MSB. Shifts the contents of the AC right and enter 1 into the MSB. Shifts the contents of the AC left and enter 0 into the LSB. Shifts the contents of the AC left and enter 1 into the LSB. Memory M (DP) contents incremented +1, and loaded to AC and M (DP). Memory M (DP) contents decremented -1, and loaded to AC and M (DP). AC, memory M (DP) and CF contents are binary-added and the result loaded to AC. AC, memory M (DP) and CF contents are binary-added and the result loaded to AC, M (DP). AC, immediate data and CF contents are binary-added, and the result loaded to AC. AC, memory M (DP) and CF contents are binary-subtracted, and the result loaded to AC. AC, memory M (DP) and CF contents are binary-subtracted, and the result loaded to AC and M (DP). AC, immediate data and CF contents are binary-subtracted and the result loaded to AC. AC and memory M (DP) contents are binary-added and the result loaded to AC. AC and memory M (DP) contents are binary-added and the result loaded to AC and M (DP). AC and immediate data contents are binary-added and the result loaded to AC. AC and memory M (DP) contents are binary-subtracted and the result loaded to AC. AC and memory M (DP) contents are binary-subtracted and the result loaded to AC and M (DP). AC. CF CF CF CF CF CF CF CF CF CF CF flag affected
1 1 1 1 1 1 1 1 1 1 2 1 1 2 1 1 2 1 1 2 1 1 2 1 1 2 1 1 2 1 1 2
2 1 1 1 1 1 1 1 1 1 2 1 1 2 1 1 2 1 1 2 1 1 2 1 1 2 1 1 2 1 1 2
Accumulator
0000 AC (AC)+X+CF X3X2X1X0 0001 1001 AC (AC)+[M (DP)]+CF AC, M (DP) (AC)+[M (DP)]+CF
0001 AC (AC)+X+CF X3X2X1X0 0010 1010 0010 X3X2X1X0 0011 1011 0011 X3X2X1X0 0100 1100 0100 X3X2X1X0 0101 1101 AC (AC) [M (DP)] AC, M (DP) (AC) [M (DP)] AC (AC)+[M (DP)] AC, M (DP) (AC)+[M (DP)] AC (AC)+X AC (AC)+[M (DP)]+1 AC, M (DP) (AC)+[M (DP)]+1 AC (AC)+X+1 AC (AC)+[M (DP)] AC, M (DP) (AC)+[M (DP)] AC (AC)+X
Arithmetic
ADD* ADDI X
AC and immediate data contents are binary-subtracted and the result loaded in CF AC and memory M (DP) contents are binary-added and the result loaded to AC. AC and memory M (DP) contents are binary-added and the result loaded to AC and M (DP). AC and immediate data contents are binary-added and the result loaded in AC. AC and memory M (DP) contents are ANDed and the result loaded to AC. AC and memory M (DP) contents are ANDed and the result loaded to AC and M (DP). AC and immediate data contents are ANDed and the result loaded to AC. AC and memory M (DP) are exclusive ORed and the result loaded to AC. AC and memory M (DP) are exclusive ORed, and the result loaded to AC and M (DP). AC and immediate data are exclusive ORed and the result loaded to AC. AC and memory M (DP) are ORed and the result loaded to AC. AC and memory M (DP) are ORed and the result loaded to AC and M (DP). AC and immediate data are ORed and the result loaded to AC.
0101 AC (AC) X X3X2X1X0 0110 1110 AC (AC) [M (DP)] AC, M (DP) (AC) [M (DP)]
Logical
EORI X OR OR* ORI X
0110 AC (AC) X X3X2X1X0 0111 1111 AC (AC) [M (DP)] AC, M (DP) (AC) [M (DP)]
0111 AC (AC) X X3X2X1X0
Continued on next page.
No.4144-12/16
LC573104A, 573102A
Continued from preceding page.
Instruction
Mnemonic SDPL SDPH LDPL LDPH MDPL X MDPH X EDPL EDPH IDPL IDPH DDPL DDPH SSP LSP MSP X ISP DSP LHLT L500 CSP CST Instruction code 0001 0001 1111 1111 1011 1100 0001 0001 1001 1001 1001 1001 1010 1010 1110 1001 1001 1010 1010 0000 0000 0000 0000 1111 1111 1010 1010 0011 0010 1100 1101 1101 1110 DPL (AC) DPH (AC) AC (DPL) AC (DPH) Function
Cycles
Bytes
Status Function description AC contents loaded to DPL. AC contents loaded to DPH. DPL contents loaded to AC. DPH contents loaded to AC. Immediate data X loaded to DPL. Immediate data X loaded to DPH. DPL and EDPL contents exchanged. DPH and EDPH contents exchanged. DPL contents incremented +1. DPH contents incremented +1. DPL contents decremented -1. DPH contents decremented -1. AC contents loaded to SP. SP contents loaded to AC. Immediate data X loaded to SP. SP contents incremented +1. SP contents decremented -1. STS2 contents loaded to AC and STS2 is reset. STS1 contents loaded to AC and SCF0 is reset. CSTF reset. CSTF set. HEF0 reset to inhibit Halt mode release by overflow from the divider circuit. HEF0 set enabling overflow from the divider circuit to release the Halt mode. CF reset. CF set. Memory M (DP) contents transferred to AC. AC contents stored in memory M (DP). Immediate data X loaded to AC. Immediate data X loaded to memory M (DP). SCF1 to SCF4 SCF0 CSTF CSTF HEF0 HEF0 CF CF flag affected
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
X3X2X1X0 DPL X X3X2X1X0 DPH X 1110 1111 1010 1100 1011 1101 1110 1010 (DPL) (EDPL) (DPH) (EDPH) DPL (DPL)+1 DPH (DPH)+1 DPL (DPL)-1 DPH (DPH)-1 SP (AC) AC (SP)
Data Pointer
SP
X3X2X1X0 SP X 1110 1111 1011 1100 0100 0101 0110 0111 0000 0001 1001 1101 SP (SP)+1 SP (SP)-1 AC (STS2), STS2 0 AC (STS1), SCF0 0 CSTF 0 CSTF 1 HEF0 0 HEF0 1 CF 0 CF 1 AC [M (DP)] M (DP) (AC)
Flag Data transfer
RC5 SC5 RCF SCF LDA STA LDI X MVI X
X3X2X1X0 AC X X3X2X1X0 M (DP) X
Continued on next page.
No.4144-13/16
LC573104A, 573102A
Continued from preceding page.
Instruction Mnemonic HALT SCI X Instruction code 0000 1101 0000 Function CPU operation halts Function description * Halts CPU operation. HALT mode is released under the following conditions. * HALT mode is cancelled by the interaction of SIC X and SC5 commands. X0 to X3 Operation. X0 CPU control X1 X2 X3 NOP IPS IPM SPDR X 1111 1010 1010 1111 1111 1111 1000 0 1 X 1X0 No operation AC [P (S)] AC [P (M)] PDF X 1 1 1 1 1 1 1 1 HFE1 is set to enable release of HALT mode by overflow signal from divider circuit following CF oscillation circuit. HFE2 is set enabling signal rise at input port S to release HALT mode. HFE3 is set enabling signal rise at input port M to release HALT mode. HFE4 is set enabling 1/10 second pulse to release HALT. HEF1 to HEF4 Status flag affected Cycles 1 1 No operation. Input data at input port S loaded to AC. Input data at input port M loaded to AC. Pull-down resister MOS-Tr at corresponding input port turned ON/OFF. Bit content X0=0 X0=1 X1=0 X1=1 Input/Output OUT 1111 1100 (1) Cannot be used when SPC =0&SP=0H to CH, EH, FH. (2) When SP=0&SP=D CTL3 (AC) (3) When SPC=1 SFR (AC) TWRT 0000 0010 (1) Cannot be used when SPC =0&SP=0H to CH, EH, FH. (2) When SPC=0&SP=D CTL3 ROM (3) When SPC=1 SFR ROM 1 1 1 1 Operation S-Terminal Pull down Tr OFF. S-Terminal Pull down Tr ON. M-Terminal Pull down Tr OFF. M-Terminal Pull down Tr ON. PDF Bytes 1 1
X3X2X1X0 CTL2 X
Cannnot be used. (Causes error when OUT is executed at SPC=0&SP=0H to CH, EH, FH.) AC contents transferred to CTL3. AC contents transferred to special function register SFR. Cannnot be used. (Causes error when TWRT is executed at SPC=0&SP=0H to CH, EH, FH.) High-order 4 bits data of ROM, on current page, addressed by PC whose loworder 8 bits are replaced by AC and M (DP) contents, is transferred to CTL3. High-order 4 bits or 8 bits data of ROM, on the current page, addressed by PC whose low-order 8 bits are replaced by AC and M (DP) contents is transferred to special function register SFR CFCF CCF CFCF CCF
IN
0001
0111
(1) Cannot be used at SPC =0&SP=0H to CH, EH, FH. (2) When SPC=0&SP=D AC (STS3) (3) When SPC=1 AC (SFR)
1
1
Cannnot be used. (Causes error when IN is executed at SPC=0&SP=0H to CH, EH, FH.) STS3 contents transferred to AC. Special function register SFR contents transferred to AC.
Continued on next page.
No.4144-14/16
LC573104A, 573102A
Continued from preceding page.
Instruction
Mnemonic JMP X BAB0 X BAB1 X BAB2 X BAB3 X BAZ X BANZ X BCNH X BCH X PAGE JMP* Instruction code 0000 1 X10X9X8 Function (PC10 to PC0) X10 to X0 If AC0=1 then If AC1=1 then If AC2=1 then If AC3=1 then If AC=0 then (PC10 to PC0) X10 to X0 If AC0 then (PC10 to PC0) X10 to X0 If CF1 then (PC10 to PC0) X10 to X0 If CF=1 then (PC10 to PC0) X10 to X0 PAGE [M (DP)] PC10 to PC08 (PAGE) PC07 to PC04 (AC) PC11 0 PC11 1 STACK (PC)+2 (PC10 to PC0) X10 to X0 PC (STACK) SPC 0 SPC 1 11 to 15 0 (WDT) 0 2 1 1 2 1 1 2 2 2 2
Cycles
Bytes
Status Function description Loads data specified by X10 to X0 to PC and jumps unconditionally. When AC bit 0 is '1', data specified by X10 to X0 is loaded to PC and jumps. At '0', PC is incremented +2. When AC bit 1 is '1', data specified by X10 to X0 is loaded to PC and jumps. At '0', PC is incremented +2. When AC bit 2 is '1', data specified by X10 to X0 is loaded to PC and jumps. At '0', PC is incremented +2. When AC bit 3 is '1', data specified by X10 to X0 is loaded to PC and jumps. At '0', PC is incremented +2. When AC is '0', data specified by X10 to X0 is loaded to PC and jumps. When AC is not '0', PC is incremented +2. When AC is not '0', data specified by X10 to X0 is loaded to PC and jumps. When AC is '0', PC is incremented +2. When CF is '0', data specified by X10 to X0 is loaded to PC and jumps. When CF is '1', PC is incremented +2. When CF is '1', data specified by X10 to X0 is loaded to PC and jumps. When CF is '0', PC is incremented +2. Memory M (DP) contents loaded to PAGE latch. Unconditionally jumps to page specified by PAGE and address whose loworder 8 bits are specified by contents of AC and memory M (DP). Select ROM bank 0. Select ROM bank 1. Current PC+2 contents are saved in STACK, data specified by X10 to X0 is loaded to PC and sub-routine is called. Returns PC contents saved in STACK to PC and returns from sub-routine. Resets strobe pointer control bit (SPC) to '0'. Sets strobe pointer control bit (SPC) to '1'. Resets high-order 4 bits of divider circuit. Resets Watchdog Timer counter. SPC SPC SCF0 SCF4 flag affected
2 2 2 2 2 2
2 2 2 2 2 2
X7X6X5X4 X3X2X1X0 0100 1 X10X9X8 X7X6X5X4 X3X2X1X0 0101 1 X10X9X8 X7X6X5X4 X3X2X1X0 0110 1 X10X9X8 X7X6X5X4 X3X2X1X0 0111 1 X10X9X8 X7X6X5X4 X3X2X1X0 0100 0 X10X9X8 X7X6X5X4 X3X2X1X0 0101 0 X10X9X8 X7X6X5X4 X3X2X1X0 0110 0 X10X9X8 X7X6X5X4 X3X2X1X0 0111 0 X10X9X8 X7X6X5X4 X3X2X1X0 0001 0001 0001 0000
(PC10 to PC0) X10 to X0 (PC10 to PC0) X10 to X0 (PC10 to PC0) X10 to X0 (PC10 to PC0) X10 to X0
Branching/subroutine
PC03 to PC00 [M (DP)] 2 2 2 1 2 2 1 1 2 2 2 1 2 2 1 1
ROM0 ROM1 JSR X RST SPC0
1100 0010 1100 0010
1000 0000 1000 0001
1010 0 X10X9X8 X7X6X5X4 X3X2X1X0 0001 0011 1100 0010 1100 0010 1111 1111 1001 0000 1001 0001 1011 1001
Miscellaneous
SPC1 CSEC RWDT
No.4144-15/16
LC573104A, 573102A
LC573100 Series Instructions Map
Lower 0 Uppwer 0 1 2 3 4 5 6 7 8 9 A B C D E F RCF SCF NOP NOP SPDR X MDPH X - ADC ADCI SBC SBCI ADD ADDI BAZ X BCNH X BCNH X BCH X SUB SUBI ADN ADNI AND ANDI EOR EORI OR ORI ADC* INC IPM MDPL X ROMX SPCX SIC X MSP X - RWDT - CSEC OUT LDPL LDPH NOP - SBC* DEC LDA ADD* IDPL LSP HALT JMP* TAAT PAGE TWRT MTR - RTS CSP - CST - RC5 - SC5 IN ASR0 MVI X LDI X BAB0 X BAB1 X BAB2 X BAB3 X SUB* DDPL LHLT ADN* IDPH L500 AND* DDPH STA EOR* ISP SSP OR* DSP IPS ASR1 ASL0 JMP X ASL1 SDPL SDPH EDPL EDPH 1 2 3 4 5 6 7 8 9 A B C D E F
JSR X
XXX : 1 Byte-1 Cycle instruction XXX : 2 Byte-2 Cycle instruction
ROMX : ROM0 instruction (C820H), ROM1 instruction (C821H) SPCX : SPC0 instruction (C920H), SPC1 instruction (C921H)
XXX : 1 Byte-2 Cycle instruction
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products(including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be expor ted without obtaining the expor t license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of October, 2001. Specifications and information herein are subject to change without notice.
PS No.4144-16/16

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